person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives.
Come join us and do something wonderful! Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver Mixed Signal solutions for products that impact customers lives? If so, come join us to do something wonderful. CEG (Client Engineering Group) designs and delivers the full range of client compute solutions on leading edge processes. The memory
interface team within CEG develops cutting-edge high-speed memory interface designs such as LPDDR and DDR for use in Intel's latest microprocessors. We own the design from architecture definition to tape-out and Post Silicon support covering all aspects of a Mixed Signal design from Analog circuit to RTL development and structural implementation.
You will be responsible for, but not limited to: We are looking for a versatile engineer who is familiar with both analog circuit design and RTL coding. This individual will be responsible for understanding circuit architecture documentation and translating architectural intent into behavioral model in System Verilog for analog circuits. The
individual will then integrate and turn in the behavioral model into the PHY RTL repo and resolve logic simulation failures.
The individual will also work with analog circuit designers who translated architecture intent into schematics, and confirm the behavioral model and schematics are functionally equivalent. Experience in designing, developing, and building analog circuits in advanced process nodes for analog and mixed-signal IP's will be helpful. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications: BS degree + 1 years' experience minimum, or MS degree Preferred Qualifications: Transistor-level design experience Logic design experience HDL coding and verification experience, particularly with System Verilog Proven track record on design of high-speed analog and mixed-signal circuits. Understanding of architecture and integration aspects of DDR PHYs. Familiarity of LPDDR/DDR JEDEC specifications and related DDR Protocols. Understanding of design for yield and exposure to production challenges in latest technology process node. Experience with industry standard tools for Analog design such as Cadence ADE, Spectre, AMS verification, FEV, Star RC etc.
Experience with Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation. Other Locations US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $88,320.00-$132,660.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0254793pca3lyuhf
person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives.
Come join us and do something wonderful! Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver Mixed Signal solutions for products that impact customers lives? If so, come join us to do something wonderful. CEG (Client Engineering Group) designs and delivers the full range of client compute solutions on leading edge processes. The memory
team within CEG develops cutting-edge High-Speed IO designs like LPDDR5, DDR5, PCIE Gen7, USB and Type C Phys for use in Intel's latest microprocessors. We own the design from architecture definition to tape-out and Post Silicon support covering all aspects of a Mixed Signal design from Analog circuit to RTL development and structural implementation.
You will be responsible for, but not limited to: We are looking for an organized person with strong static timing analysis skills to run timing characterization for analog and mixed-signal circuits. The ideal candidate will have automation background which enables him/her to monitor and execute on many blocks concurrently. The candidate also
should be methodical to ensure data consistency and correctness for the many circuits being analyzed across many different process/voltage/temperature corners.
The candidate will also be expected to perform of perform static timing analysis on high-speed data path and clock crossings using industry standard STA tools. Experience in designing, developing, and building analog circuits in advanced process nodes for analog and mixed-signal IP's will be helpful. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications: BS degree plus 4 years' experience minimum, or MS degree plus 3 years' experience minimum, or Ph D plus 1 year experience minimum AND Experience doing static timing analysis work. Preferred Qualifications: Programming/scripting/automation skills Experience with analog circuit and/or standard cell characterization Good organization skills and ability to execute many instances of similar task concurrently. Understanding of architecture and integration aspects of DDR PHYs. Familiarity of LPDDR/DDR JEDEC specifications and related DDR Protocols.
Understanding of design for yield and exposure to production challenges in latest technology process node. Experience with industry standard tools such as Prime Time. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Other Locations US, OR, Hillsboro; US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $139,480.00-$209,760.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0254815pca3lyuhf
planning and permitting, measurement and analytical services, and environmental resiliency and sustainability solutions. Our qualified engineers, scientists, technicians, associates, and policy experts are proud of our collective expertise and the collaborative nature of our approach to helping clients.
We strive to optimize environmental resiliency in a way that effectively complements our clients' decision-making and operations and efficiently fulfills their project requirements. We have over 90 offices across the United States, Canada, Europe, and Australia and are approaching 3500 employees - all ready to provide solutions for environmental needs. The Environmental Engineering and
Consulting team delivers solutions for complex environmental challenges using our regulatory expertise and implementing practical and cost-effective compliance management processes and programs.
We address our clients' biggest concerns around permitting, ecoservices, backssment, and remediation. Our highly trained and experienced engineers and scientists, environmental and remediation specialists, geologists, hydrogeologists, biologists, and environmental compliance specialists work with both public- and private-sector clients, delivering turnkey solutions. A DAY IN THE LIFEOur NEPA Specialist (Senior Environmental Professional) position is located in California and can be performed remotely
within the state. As a key senior member of the team, this role will be responsible for a full range of activities, including: Prepare and manage the preparation of CEQA and NEPA documents, including Initial Studies, Negative Declarations, Environmental Impact Reports, Environmental backssments, Environmental Impact Statements, and supporting technical studies.
Provide environmental planning knowledge and project management to help with environmental impact analysis, coordination on biological and culturalassessment support, CEQA/NEPA research and document production support, tribal fees totrust projects andcoordination for other associated environmental projects.
The selected candidate will assist in data gathering, conducting impact analyses, writing sections for CEQA/NEPA documents, assisting in preparing permit applications, coordinating with sub-consultants and project team members, and interacting with regulatory agencies. Identify, evaluate, and solve environmental compliance and regulatory issues related to planning, energy, infrastructure, and public works projects. Manage and oversee multiple projects simultaneously within scope, schedule and budget expectations. Take an active leadership role in the development of new business with new and existing clients.
Develop and expand client relationships that generate repeat business. Prepare proposals, interview, and win large energy, infrastructure, and public works projects from federal, state, and local municipal clients. Maintain confidentiality at all times. Exercise safe work practices by following all Company safety rules and OSHA regulations, including attendance at all required safety training programs. Participate in the company's continuous improvement programs and provide support toteam efforts. Keep up-to-date and current on industry trends by completing formal training, reviewingprofessional publications, and attending professional workshops.
Perform other duties as assigned. Provide leadership, training, and mentorship to team members. YOUR EXPERTISE AND SKILLSTo perform this job successfully, individuals must be able to perform each duty and responsibility satisfactorily. The requirements listed below are representative of the knowledge, skill, and/or ability required. Bachelor and Master's degree in Environmental Planning, Environmental Studies, or a related field. 15 to 20 years of experience in environmental planning. AICP, LEED AP, or CEP certifications are a plus 10 years of experience managing large projects/programs for federal and state agencies, utilities, municipalities, and counties.
The candidate should have direct experience and knowledge of environmental regulations, assisting in research for NEPA and CEQA planning documents, preparing or assisting in the preparation of technical sections, and knowledge of environmental permits (CWA 404/401, NHPA 106, ESA Section 7). Preference will be given to candidates with NEPA experiencewriting EAs Experience with air quality evaluations, sustainability planning, and preparing technicalreports is a plus.
Strong research, analysis, and reporting abilities. Focus on detail-orientation skills and capable of managing large data sets. Are self-starting, team-oriented professionals with excellent written and communication skills. Should be familiar with review and analysis of scientific data, maps, and drawings, and have NEPA experience. Knowledge of computer-aided software (Microsoft Suite, Google Suite, Auto CAD, Arc GIS, etc. ) Ability to define problems, collect data, establish facts, and draw valid conclusions topresent to supervisors. Organizational skills and attention to detail.
While performing the responsibilities of the job, the employee may be required to spend longhours sitting and using office equipment and computers and is regularly required to sit, talk, and hear. The employee is frequently required to use hands and fingers to handle or feel. There may be occasional lifting (overhead, waist level) from the floor of supplies andmaterials weighing no more than 30 pounds. The work may involve some bending, standing, or walking. Out-of-office site visits could potentially have more strenuous physical demands. The work environment will vary greatly depending on the nature of assigned tasks.
Possible work environments could include normal office working conditions in a well-lit, climate-controlled environment with minimal safety/health hazard potential. The position may involve local travel as needed. WHAT WE CAN OFFER YOU As a key member of our Montrose team, you can expect: Mentorship and professional development resources to advance your career Direct exposure to our industry's leading experts who are solving the world's toughest environmental challenges An entrepreneurial environment where you can learn, thrive and collaborate with talented colleagues Opportunities to engage and contribute in our Diversity, Fairness and Inclusion and Women Empowering Leadership employee resource groups Competitive compensation package: annual salary ranging from $130,000 to $170,000 commensurate with accomplishments, performance, credentials and geography Competitive medical, dental, and vision insurance coverage 401k with a competitive 4% employer match Progressive vacation policies, company holidays and paid parental leave benefits to ensure work/life balance A financial assistance program that supports peers in need, known as the Montrose Foundation Access to attractive student loan rates to optimize your student loan payoff plans The above statements are intended to describe the general nature of work being performed by people assigned to this classification.
They are not to be construed as an exhaustive list of all responsibilities, duties, and skills required of employees so classified. If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact 949-988-xyz X or xyz X@montrose- for assistance.
MAKE THE MOVE TO ACCELERATE YOUR CAREERWe are a fast-paced, dynamic, and high-growth company. You will have the freedom to make decisions and be your own boss while receiving support from talented and knowledgeable colleagues and service providers. Want to know more about how we can help you take your career to the next level? Visit us at montrose-! Montrose is an Equal Opportunity Employer. Montrose is committed to recruiting and hiring qualified candidates without regard to race, religion, interaction, interactionual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.
Montrose is committed to providing access and reasonable accommodation in its employment for individuals with disabilities. #INDMEG
delivering projects related to local agency bridges and possess a strong understanding of the HBP (Local Highway Bridge Program). Responsibilities: Lead and contribute to the design and analysis of local agency bridge projects. Collaborate with multidisciplinary teams to ensure successful project delivery.
Conduct structural analyses, prepare calculations, and develop detailed design plans. Review and interpret project specifications, codes, and regulatory requirements. Provide technical expertise and guidance to junior engineers as needed. Participate in project meetings, communicate with clients, and address project-related issues. Qualifications: Bachelor's degree in civil engineering
or a related field. Professional Engineer (PE) license in the state of California. Minimum of 5 years of progressive design experience, with a focus on bridge engineering.
Proven experience in delivering local agency bridge projects. Familiarity with the HBP (Local Highway Bridge Program) in California is a plus. Strong proficiency in relevant design software and engineering tools. Excellent communication and interpersonal skills. Ability to work independently and collaboratively within a team. Salary (DOE): $90,000 - $130,000 Why Ardurra? While Ardurra offers competitive compensation and rich benefits programs, it is our culture that truly sets us apart from our peers. We nurture
a family-like culture, striving to create a work environment that is enjoyable, challenging and rewarding but also fun.
We are acutely focused on developing our staff, whether through our internal Ardurra Academy or through our industry-leading Leadership program. We have made a deliberate and focused commitment to nurture a people-centric culture where people are: valued as individuals; supported in their professional and career development with multiple, varied career paths; provided the tools and resources to be successful, engaged, and satisfied in their work; and positive benefits, time-off programs, and flexibility to help maintain a healthy balance between work and home.
Ardurra is an Equal Opportunity/ Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, interaction, national origin, disability, protected veteran status, gender identity or interactionual orientation. NOTICE TO THIRD PARTY AGENCIES: Ardurra does not accept unsolicited resumes from recruiters or employment agencies. In the absence of a signed Agency Agreement, Ardurra will not consider or agree to payment of any referral compensation or recruiter fee. If a resume or candidate is submitted to any hiring manager without a previously signed agreement, Ardurra reserves the right to pursue and hire those candidate(s) without any financial obligation to the recruiter or agency.
These candidates will be considered property of Ardurra. We’re not currently looking to add any more agencies to our list of approved vendors, so please do not contact any of our managers or recruitment team with sales calls or details of your candidates. Equal Opportunity Employer/Protected Veterans/Individuals with Disabilities The contractor will not discharge or in any other manner discriminate against employees or applicants because they have inquired about, discussed, or disclosed their own pay or the pay of another employee or applicant.
However, employees who have access to the compensation information of other employees or applicants as a part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information, unless the disclosure is (a) in response to a formal complaint or charge, (b) in furtherance of an investigation, proceeding, hearing, or action, including an investigation conducted by the employer, or (c) consistent with the contractor’s legal duty to furnish information.
41 CFR 60-1.35(c)
Controls Engineer – Automation Our Controls Engineers perform engineering, specification, design, testing and commissioning of Programmable Logic Controllers (PLCs), Distributed Control Systems (DCSs) and Human Machine Interface (HMI) based automation control systems that integrate hardware and software for large industrial project applications, specifically in the metals industry.
OPPORTUNITIES IN: ALPHARETTA, GA and CANONSBURG, PASIGN ON BONUS RELOCATIONControls Engineers also provide technical solutions, process know-how, customer training, and service support on large industrial processes, including electrical, mechanical, and metallurgical processes, for rolling and processing of
metals for industrial customers, domestic and international. Position Overview: Engineering, designing, and integrating automation and control systems for the metals industry Designs complex systems that integrate hardware and software.
Develops material specification, schematic preparation, and the appropriate follow-up Generates recommendations for productivity improvement and cost reduction Guides technical knowledge interchange for both processes and applications to system design Required Skills/Knowledge, Education and Experience: BS/AS in related engineering or technology degree5+ years experience of engineering to resolve complex problems not covered by existing procedures or practices
Work on and with international and domestic teams Must be able to travel Hours/Benefits/Compensation: Hybrid Schedule Full range of benefits starting 1st day of employment, including Medical/Dental/Vision, Life, Short Term Disability, 401K with 6% match, 3 weeks PTOCompetitive pay A HOME FOR PIONEERS, TECHNOLOGY ENTHUSIASTS, AND TEAM PLAYERSPrimetals is an Equal Opportunity and Affirmative Action Employer encouraging diversity in the workplace.
All qualified applicants will receive consideration for employment without regard to their race, color, creed, religion, ancestry, national origin, interaction, interactionual orientation, gender identity, age, marital status, family responsibilities, pregnancy, genetic information, protected veteran or military status, other categories protected by federal, state, or local law, and regardless of whether the qualified applicants are individuals with disabilities.
For more details: jobs-search. org/controls-engineer_sacramento-c426438/controls-engineer-sacramento_i1969881256
right person to take a CAD RV Flow and Methodology Engineer role in the creation and validation of EM, IR, Thermo, ESD, HV-EOS sign-off flows and tool certification. You will be responsible for, but not limited to: Develops and applies computer aided design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems.
backssing architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design
specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.
Working with external vendors and internal teams to develop industry standard ASIC and Custom EM, IR, RV-Thermal, Power-Thermal, ESD and HV-EOS sign-off flows. Working with internal teams and external vendors on tool certification, definition of certification criteria, and definition of required test benches. In addition to the qualifications listed below the ideal candidate will also have: Excellent communication: Expected to drive clarity across customers,
stakeholders, partners, managers by clearly and concisely summarizing problems, status, data, and proposals both orally and in writing.
Excellent teamwork: With a relatively small team, we need everyone to help however and wherever they can. This means being flexible in assignment as dictated by program needs. Eagerness to learn: Initially the focus will be on specific RV flow, but ultimately the role will expand to whatever is necessary to help IFS to succeed in development of RV flows. Qualifications Minimum Qualifications: BSEE or similar degree with 1+ years of prior relevant experience OR MSEE or similar degree. 3+ months experience with custom and ASIC EDA tools.
3+ months experience with custom and/or ASIC Circuit design. Preferred Qualifications: Basic device physics understanding. Excellent written and verbal communication. Familiarity writing Python, C-Shell, and PERL Scripting. Experience with Ansys Totem, Cadence Voltus-Fi/Voltus, Ansys RHSC, Open Rail tools/flows. Inside this Business Group Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first " Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.
Other Locations US, AZ, Phoenix; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $80,190.00-$120,050.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0251615pca3lyuhf
test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient, and sustainable source of supply. This job opportunity in IFS will be part of the Customer Solutions Engineering (CSE) group which is responsible for the portions of the system foundry that brings the best of Intel technologies to IFS customers, differentiating and accelerating their solutions from architecture to post-silicon validation.
The role of a Senior Design Verification Engineer includes but is not limited to: Developing pre-Silicon functional validation tests to verify system will meet design requirements. Creating test
plans for RTL validation Defining and running system simulation models Finding and implementing corrective measures for failing RTL tests. Analyzing and using results to modify testing.
Mentoring and coaching team members Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in electrical engineering, computer engineering, computer science, or in any STEM related field of study with 6+ years of experience in Design Verification Developing UVM and/or Formal-based
verification architectures and methodologies. 4+ yrs. experience in Hardware Design Language (such as VHDL or Verilog).
4+ yrs. exp. In C/C++ programming 4+ yrs. experience with scripting languages Low power experience (e. g. UPF) Formal verification experience and debugging. Preferred Qualifications: Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree. Experience in analog and/or digital design Experience with DDR, Ethernet and/or PCIe protocols Fluent in writing protocols, compiling, Hardware verification, and firmware. #IFSJobs Inside this Business Group Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs.
With the first " Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.
Annual Salary Range for jobs which could be performed in US, California: $139,480.00-$209,760.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0254660pca3lyuhf
building a better tomorrow. Want to learn more? Visit our You Tube Channel or the links below! Life at Intel Diversity at Intel You will be part of Graphics IP Design Enabling Team and working on innovative technologies to improve design efficiency and quality.
As a Senior Logic Design Methodology Engineer you will design, develop, test, and debug software tools, flows, and methodologies used in design automation. You will work with other engineer teams to design hardware products, process design, or in manufacturing. Responsibilities and skills will include but are not limited to: Capturing user requirements, writing both functional and test code, automating build and deployment, and/or
performing unit, integration, and end-to-end testing of the software tools. Working with the customers on easy integration of IP in their environment. Coordinate with multiple teams to optimize IP delivery and ease of integration.
Very good communication skills Good at working with diverse and distributed teams Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelors Degree in Computer Science, Electrical engineering, or a related STEM degree and 15 plus year of experience
in three or more of the following: Experience working in EDA tools, flows, methodologies Experience working in complex IP/So C design development environment Knowledge of System Verilog, RTL simulation and static checks Knowledge of data-structures/algorithms Programming languages to include C/C++ and scripting in either Perl/Python/TCL Preferred Qualifications: Masters Degree or higher in Computer Science, Electrical engineering, or a related STEM degree Design verification and validation and debugging experience Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones.
Working with our partners across the industry, we intend to continue to advance PC experiences to deliver the real-world performance people demand. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.
Other Locations US, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, interaction, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, interactionual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $156,410.00-$250,410.00Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0254602pca3lyuhf
